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PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
Rev. 08 -- 22 October 2009 Product data sheet
1. General description
The PCA9555 is a 24-pin CMOS device that provides 16 bits of General Purpose parallel Input/Output (GPIO) expansion for I2C-bus/SMBus applications and was developed to enhance the NXP Semiconductors family of I2C-bus I/O expanders. The improvements include higher drive capability, 5 V I/O tolerance, lower supply current, individual I/O configuration, and smaller packaging. I/O expanders provide a simple solution when additional I/O is needed for ACPI power switches, sensors, push buttons, LEDs, fans, etc. The PCA9555 consists of two 8-bit Configuration (Input or Output selection); Input, Output and Polarity Inversion (active HIGH or active LOW operation) registers. The system master can enable the I/Os as either inputs or outputs by writing to the I/O configuration bits. The data for each Input or Output is kept in the corresponding Input or Output register. The polarity of the read register can be inverted with the Polarity Inversion register. All registers can be read by the system master. Although pin-to-pin and I2C-bus address compatible with the PCF8575, software changes are required due to the enhancements, and are discussed in Application Note AN469. The PCA9555 open-drain interrupt output is activated when any input state differs from its corresponding input port register state and is used to indicate to the system master that an input state has changed. The power-on reset sets the registers to their default values and initializes the device state machine. Three hardware pins (A0, A1, A2) vary the fixed I2C-bus address and allow up to eight devices to share the same I2C-bus/SMBus. The fixed I2C-bus address of the PCA9555 is the same as the PCA9554, allowing up to eight of these devices in any combination to share the same I2C-bus/SMBus.
2. Features
I I I I I I I I I I I Operating power supply voltage range of 2.3 V to 5.5 V 5 V tolerant I/Os Polarity Inversion register Active LOW interrupt output Low standby current Noise filter on SCL/SDA inputs No glitch on power-up Internal power-on reset 16 I/O pins which default to 16 inputs 0 Hz to 400 kHz clock frequency ESD protection exceeds 2000 V HBM per JESD22-A114, 200 V MM per JESD22-A115, and 1000 V CDM per JESD22-C101
NXP Semiconductors
PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
I Latch-up testing is done to JEDEC Standard JESD78 which exceeds 100 mA I Six packages offered: DIP24, SO24, SSOP24, TSSOP24, HVQFN24 and HWQFN24
3. Ordering information
Table 1. Ordering information Name PCA9555N PCA9555D PCA9555DB DIP24 SO24 SSOP24 Description plastic dual in-line package; 24 leads (600 mil) plastic small outline package; 24 leads; body width 7.5 mm plastic shrink small outline package; 24 leads; body width 5.3 mm plastic thin shrink small outline package; 24 leads; body width 4.4 mm plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm Version SOT101-1 SOT137-1 SOT340-1 SOT355-1 SOT616-1 SOT994-1 Type number Package
PCA9555PW TSSOP24 PCA9555BS PCA9555HF HVQFN24
HWQFN24 plastic thermal enhanced very very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.75 mm
3.1 Ordering options
Table 2. PCA9555N PCA9555D PCA9555DB PCA9555PW PCA9555BS PCA9555HF Ordering options Topside mark PCA9555 PCA9555D PCA9555 PCA9555 9555 P55H Temperature range -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C -40 C to +85 C Type number
PCA9555_8
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 08 -- 22 October 2009
2 of 34
NXP Semiconductors
PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
4. Block diagram
PCA9555
8-bit INPUT/ OUTPUT PORTS
IO1_0 IO1_1 IO1_2 IO1_3 IO1_4 IO1_5 IO1_6 IO1_7
A0 A1 A2
write pulse read pulse I2C-BUS/SMBus CONTROL
SCL SDA
INPUT FILTER 8-bit INPUT/ OUTPUT PORTS
IO0_0 IO0_1 IO0_2 IO0_3 IO0_4 IO0_5 IO0_6 IO0_7 VDD LP filter INT
write pulse read pulse POWER-ON RESET
VDD VSS
002aac702
Remark: All I/Os are set to inputs at reset.
Fig 1.
Block diagram of PCA9555
5. Pinning information
5.1 Pinning
INT A1 A2 IO0_0 IO0_1 IO0_2 IO0_3 IO0_4 IO0_5
1 2 3 4 5 6 7 8 9
24 VDD 23 SDA 22 SCL 21 A0 20 IO1_7 19 IO1_6 18 IO1_5 17 IO1_4 16 IO1_3 15 IO1_2 14 IO1_1 13 IO1_0
002aac697
INT 1 A1 2 A2 3 IO0_0 4 IO0_1 5 IO0_2 6 IO0_3 7 IO0_4 8 IO0_5 9 IO0_6 10 IO0_7 11 VSS 12
002aac698
24 VDD 23 SDA 22 SCL 21 A0 20 IO1_7 19 IO1_6 18 IO1_5 17 IO1_4 16 IO1_3 15 IO1_2 14 IO1_1 13 IO1_0
PCA9555N
PCA9555D
IO0_6 10 IO0_7 11 VSS 12
Fig 2.
PCA9555_8
Pin configuration for DIP24
Fig 3.
Pin configuration for SO24
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 08 -- 22 October 2009
3 of 34
NXP Semiconductors
PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
INT A1 A2 IO0_0 IO0_1 IO0_2 IO0_3 IO0_4 IO0_5
1 2 3 4 5 6 7 8 9
24 VDD 23 SDA 22 SCL 21 A0 20 IO1_7 19 IO1_6 18 IO1_5 17 IO1_4 16 IO1_3 15 IO1_2 14 IO1_1 13 IO1_0
002aac699
INT A1 A2 IO0_0 IO0_1 IO0_2 IO0_3 IO0_4 IO0_5
1 2 3 4 5 6 7 8 9
24 VDD 23 SDA 22 SCL 21 A0 20 IO1_7 19 IO1_6 18 IO1_5 17 IO1_4 16 IO1_3 15 IO1_2 14 IO1_1 13 IO1_0
002aac700
PCA9555DB
PCA9555PW
IO0_6 10 IO0_7 11 VSS 12
IO0_6 10 IO0_7 11 VSS 12
Fig 4.
Pin configuration for SSOP24
20 SDA 19 SCL 21 VDD 22 INT
Fig 5.
Pin configuration for TSSOP24
21 VDD 20 SDA 19 SCL 18 A0 17 IO1_7 16 IO1_6 15 IO1_5 14 IO1_4 13 IO1_3 IO1_0 10 IO1_1 11 IO1_2 12 7 8 IO0_7 9 VSS
002aac881
24 A2 1 2 3 4 5 6 IO0_6
24 A2
23 A1
terminal 1 index area IO0_0 IO0_1 IO0_2 IO0_3 IO0_4 IO0_5 1 2 3 4 5 6
18 A0 17 IO1_7 16 IO1_6 15 IO1_5 14 IO1_4 13 IO1_3 IO1_0 10 IO1_1 11 IO1_2 12 7 8 9
IO0_0 IO0_1 IO0_2 IO0_3 IO0_4 IO0_5
PCA9555BS
PCA9555HF
IO0_6
IO0_7
VSS
002aac701
Transparent top view
Transparent top view
Fig 6.
Pin configuration for HVQFN24
Fig 7.
Pin configuration for HWQFN24
PCA9555_8
23 A1
terminal 1 index area
22 INT
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 08 -- 22 October 2009
4 of 34
NXP Semiconductors
PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
5.2 Pin description
Table 3. Symbol Pin description Pin DIP24, SO24, SSOP24, TSSOP24 INT A1 A2 IO0_0 IO0_1 IO0_2 IO0_3 IO0_4 IO0_5 IO0_6 IO0_7 VSS IO1_0 IO1_1 IO1_2 IO1_3 IO1_4 IO1_5 IO1_6 IO1_7 A0 SCL SDA VDD
[1]
Description HVQFN24, HWQFN24 22 23 24 1 2 3 4 5 6 7 8 9[1] 10 11 12 13 14 15 16 17 18 19 20 21 address input 0 serial clock line serial data line supply voltage supply ground port 1 input/output interrupt output (open-drain) address input 1 address input 2 port 0 input/output
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
HVQFN and HWQFN package die supply ground is connected to both the VSS pin and the exposed center pad. The VSS pin must be connected to supply ground for proper device operation. For enhanced thermal, electrical, and board-level performance, the exposed pad needs to be soldered to the board using a corresponding thermal pad on the board, and for proper heat conduction through the board thermal vias need to be incorporated in the PCB in the thermal pad region.
PCA9555_8
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 08 -- 22 October 2009
5 of 34
NXP Semiconductors
PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
6. Functional description
Refer to Figure 1 "Block diagram of PCA9555".
6.1 Device address
slave address 0 1 0 0 A2 A1 A0 R/W
fixed
programmable
002aac219
Fig 8.
PCA9555 device address
6.2 Registers
6.2.1 Command byte
The command byte is the first byte to follow the address byte during a write transmission. It is used as a pointer to determine which of the following registers will be written or read.
Table 4. Command 0 1 2 3 4 5 6 7 Command byte Register Input port 0 Input port 1 Output port 0 Output port 1 Polarity Inversion port 0 Polarity Inversion port 1 Configuration port 0 Configuration port 1
PCA9555_8
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 08 -- 22 October 2009
6 of 34
NXP Semiconductors
PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
6.2.2 Registers 0 and 1: Input port registers
This register is an input-only port. It reflects the incoming logic levels of the pins, regardless of whether the pin is defined as an input or an output by Register 3. Writes to this register have no effect. The default value `X' is determined by the externally applied logic level.
Table 5. Bit Symbol Default Table 6. Bit Symbol Default Input port 0 Register 7 I0.7 X 6 I0.6 X 5 I0.5 X 4 I0.4 X 3 I0.3 X 2 I0.2 X 1 I0.1 X 0 I0.0 X
Input port 1 register 7 I1.7 X 6 I1.6 X 5 I1.5 X 4 I1.4 X 3 I1.3 X 2 I1.2 X 1 I1.1 X 0 I1.0 X
6.2.3 Registers 2 and 3: Output port registers
This register is an output-only port. It reflects the outgoing logic levels of the pins defined as outputs by Registers 6 and 7. Bit values in this register have no effect on pins defined as inputs. In turn, reads from this register reflect the value that is in the flip-flop controlling the output selection, not the actual pin value.
Table 7. Bit Symbol Default Table 8. Bit Symbol Default Output port 0 register 7 O0.7 1 6 O0.6 1 5 O0.5 1 4 O0.4 1 3 O0.3 1 2 O0.2 1 1 O0.1 1 0 O0.0 1
Output port 1 register 7 O1.7 1 6 O1.6 1 5 O1.5 1 4 O1.4 1 3 O1.3 1 2 O1.2 1 1 O1.1 1 0 O1.0 1
6.2.4 Registers 4 and 5: Polarity Inversion registers
This register allows the user to invert the polarity of the Input port register data. If a bit in this register is set (written with `1'), the Input port data polarity is inverted. If a bit in this register is cleared (written with a `0'), the Input port data polarity is retained.
Table 9. Bit Symbol Default Table 10. Bit Symbol Default
PCA9555_8
Polarity Inversion port 0 register 7 N0.7 0 6 N0.6 0 5 N0.5 0 4 N0.4 0 3 N0.3 0 2 N0.2 0 1 N0.1 0 0 N0.0 0
Polarity Inversion port 1 register 7 N1.7 0 6 N1.6 0 5 N1.5 0 4 N1.4 0 3 N1.3 0 2 N1.2 0 1 N1.1 0 0 N1.0 0
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Product data sheet
Rev. 08 -- 22 October 2009
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NXP Semiconductors
PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
6.2.5 Registers 6 and 7: Configuration registers
This register configures the directions of the I/O pins. If a bit in this register is set (written with `1'), the corresponding port pin is enabled as an input with high-impedance output driver. If a bit in this register is cleared (written with `0'), the corresponding port pin is enabled as an output. Note that there is a high value resistor tied to VDD at each pin. At reset, the device's ports are inputs with a pull-up to VDD.
Table 11. Bit Symbol Default Table 12. Bit Symbol Default Configuration port 0 register 7 C0.7 1 6 C0.6 1 5 C0.5 1 4 C0.4 1 3 C0.3 1 2 C0.2 1 1 C0.1 1 0 C0.0 1
Configuration port 1 register 7 C1.7 1 6 C1.6 1 5 C1.5 1 4 C1.4 1 3 C1.3 1 2 C1.2 1 1 C1.1 1 0 C1.0 1
6.3 Power-on reset
When power is applied to VDD, an internal power-on reset holds the PCA9555 in a reset condition until VDD has reached VPOR. At that point, the reset condition is released and the PCA9555 registers and SMBus state machine will initialize to their default states. The power-on reset typically completes the reset and enables the part by the time the power supply is above VPOR. However, when it is required to reset the part by lowering the power supply, it is necessary to lower it below 0.2 V.
6.4 I/O port
When an I/O is configured as an input, FETs Q1 and Q2 are off, creating a high-impedance input with a weak pull-up to VDD. The input voltage may be raised above VDD to a maximum of 5.5 V. If the I/O is configured as an output, then either Q1 or Q2 is on, depending on the state of the Output Port register. Care should be exercised if an external voltage is applied to an I/O configured as an output because of the low-impedance path that exists between the pin and either VDD or VSS.
PCA9555_8
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 08 -- 22 October 2009
8 of 34
NXP Semiconductors
PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
data from shift register
configuration register D FF Q
Q1 100 k
output port register data VDD
data from shift register write configuration pulse write pulse
CK
Q
D FF CK
Q I/O pin
Q2
output port register
input port register D FF Q
VSS
input port register data
read pulse
CK to INT polarity inversion register
data from shift register write polarity pulse
D FF CK
Q
polarity inversion register data
002aac703
At power-on reset, all registers return to default values.
Fig 9.
Simplified schematic of I/Os
6.5 Bus transactions
6.5.1 Writing to the port registers
Data is transmitted to the PCA9555 by sending the device address and setting the least significant bit to a logic 0 (see Figure 8 "PCA9555 device address"). The command byte is sent after the address and determines which register will receive the data following the command byte. The eight registers within the PCA9555 are configured to operate as four register pairs. The four pairs are Input Ports, Output Ports, Polarity Inversion Ports, and Configuration Ports. After sending data to one register, the next data byte will be sent to the other register in the pair (see Figure 10 and Figure 11). For example, if the first byte is sent to Output Port 1 (register 3), then the next byte will be stored in Output Port 0 (register 2). There is no limitation on the number of data bytes sent in one write transmission. In this way, each 8-bit register may be updated independently of the other registers.
PCA9555_8
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 08 -- 22 October 2009
9 of 34
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Product data sheet Rev. 08 -- 22 October 2009
(c) NXP B.V. 2009. All rights reserved. PCA9555_8
NXP Semiconductors
SCL
1
2
3
4
5
6
7
8
9 command byte A 0 0 0 0 0 0 1 0 A 0.7 acknowledge from slave data to port 0 DATA 0 0.0 A 1.7 acknowledge from slave data to port 1 DATA 1 1.0 A P
slave address SDA S 0 1 0 0 A2 A1 A0 0 R/W
START condition
acknowledge from slave
STOP condition
write to port tv(Q) data out from port 0 tv(Q) data out from port 1 DATA VALID
002aac220
Fig 10. Write to Output port registers
SCL
1
2
3
4
5
6
7
8
9
16-bit I2C-bus and SMBus I/O port with interrupt
data to register slave address SDA S 0 1 0 0 A2 A1 A0 0 R/W A 0 0 command byte 0 0 0 1 1 0 A acknowledge from slave MSB DATA 0 LSB A MSB
data to register LSB DATA 1 A P
START condition
acknowledge from slave
acknowledge from slave
STOP condition
002aac221
Fig 11. Write to Configuration registers
PCA9555
10 of 34
NXP Semiconductors
PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
6.5.2 Reading the port registers
In order to read data from the PCA9555, the bus master must first send the PCA9555 address with the least significant bit set to a logic 0 (see Figure 8 "PCA9555 device address"). The command byte is sent after the address and determines which register will be accessed. After a restart, the device address is sent again, but this time the least significant bit is set to a logic 1. Data from the register defined by the command byte will then be sent by the PCA9555 (see Figure 12, Figure 13 and Figure 14). Data is clocked into the register on the falling edge of the acknowledge clock pulse. After the first byte is read, additional bytes may be read but the data will now reflect the information in the other register in the pair. For example, if you read Input Port 1, then the next byte read would be Input Port 0. There is no limitation on the number of data bytes received in one read transmission but the final byte received, the bus master must not acknowledge the data.
slave address SDA S 0 1 0 0 A2 A1 A0 0 R/W acknowledge from slave slave address (cont.) S 0 1 0 0 A2 A1 A0 1 R/W acknowledge from slave A A COMMAND BYTE A (cont.)
START condition
acknowledge from slave data from lower or upper byte of register MSB DATA (first byte) LSB A acknowledge from master MSB DATA (last byte) data from upper or lower byte of register LSB NA P STOP condition
(repeated) START condition
no acknowledge from master
at this moment master-transmitter becomes master-receiver and slave-receiver becomes slave-transmitter
002aac222
Remark: Transfer can be stopped at any time by a STOP condition.
Fig 12. Read from register
PCA9555_8
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 08 -- 22 October 2009
11 of 34
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Product data sheet Rev. 08 -- 22 October 2009
(c) NXP B.V. 2009. All rights reserved. PCA9555_8
NXP Semiconductors
data into port 0
data into port 1
INT tv(INT_N) SCL 1 2 3 4 5 6 7 8 R/W 9 I0.x A 7 6 5 4 3 2 1 0 A 7 6 5 I1.x 4 3 2 1 0 A 7 6 5 I0.x 4 3 2 1 0 A 7 6 5 I1.x 4 3 2 STOP condition 1 0 1 P trst(INT_N)
slave address SDA S 0 1 0
0 A2 A1 A0 1
16-bit I2C-bus and SMBus I/O port with interrupt
START condition read from port 0
acknowledge from slave
acknowledge from master
acknowledge from master
acknowledge from master
non acknowledge from master
read from port 1
002aac223
PCA9555
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte has previously been set to `00' (read Input Port register).
12 of 34
Fig 13. Read Input port register, scenario 1
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Product data sheet Rev. 08 -- 22 October 2009
(c) NXP B.V. 2009. All rights reserved. PCA9555_8
NXP Semiconductors
data into port 0
DATA 00 th(D)
DATA 01
DATA 02 tsu(D) DATA 11 th(D)
DATA 03
data into port 1
DATA 10
DATA 12 tsu(D)
INT tv(INT_N) SCL 1 2 3 4 5 6 7 8 R/W 9 I0.x A DATA 00 A acknowledge from master I1.x DATA 10 A acknowledge from master I0.x DATA 03 A acknowledge from master I1.x DATA 12 STOP condition 1 P trst(INT_N)
slave address SDA S 0 1 0
0 A2 A1 A0 1
16-bit I2C-bus and SMBus I/O port with interrupt
START condition read from port 0
acknowledge from slave
non acknowledge from master
read from port 1
002aac224
PCA9555
Remark: Transfer of data can be stopped at any moment by a STOP condition. When this occurs, data present at the latest acknowledge phase is valid (output mode). It is assumed that the command byte has previously been set to `00' (read Input Port register).
13 of 34
Fig 14. Read Input port register, scenario 2
NXP Semiconductors
PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
6.5.3 Interrupt output
The open-drain interrupt output is activated when one of the port pins changes state and the pin is configured as an input. The interrupt is deactivated when the input returns to its previous state or the Input Port register is read (see Figure 13). A pin configured as an output cannot cause an interrupt. Since each 8-bit port is read independently, the interrupt caused by Port 0 will not be cleared by a read of Port 1 or the other way around. Remark: Changing an I/O from an output to an input may cause a false interrupt to occur if the state of the pin does not match the contents of the Input Port register.
7. Characteristics of the I2C-bus
The I2C-bus is for 2-way, 2-line communication between different ICs or modules. The two lines are a serial data line (SDA) and a serial clock line (SCL). Both lines must be connected to a positive supply via a pull-up resistor when connected to the output stages of a device. Data transfer may be initiated only when the bus is not busy.
7.1 Bit transfer
One data bit is transferred during each clock pulse. The data on the SDA line must remain stable during the HIGH period of the clock pulse as changes in the data line at this time will be interpreted as control signals (see Figure 15).
SDA
SCL data line stable; data valid change of data allowed
mba607
Fig 15. Bit transfer
7.1.1 START and STOP conditions
Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW transition of the data line while the clock is HIGH is defined as the START condition (S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as the STOP condition (P) (see Figure 16).
SDA
SCL S START condition P STOP condition
mba608
Fig 16. Definition of START and STOP conditions
PCA9555_8
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 08 -- 22 October 2009
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NXP Semiconductors
PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
7.2 System configuration
A device generating a message is a `transmitter'; a device receiving is the `receiver'. The device that controls the message is the `master' and the devices which are controlled by the master are the `slaves' (see Figure 17).
SDA SCL MASTER TRANSMITTER/ RECEIVER SLAVE RECEIVER SLAVE TRANSMITTER/ RECEIVER MASTER TRANSMITTER MASTER TRANSMITTER/ RECEIVER I2C-BUS MULTIPLEXER
SLAVE
002aaa966
Fig 17. System configuration
7.3 Acknowledge
The number of data bytes transferred between the START and the STOP conditions from transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit. The acknowledge bit is a HIGH level put on the bus by the transmitter, whereas the master generates an extra acknowledge related clock pulse. A slave receiver which is addressed must generate an acknowledge after the reception of each byte. Also a master must generate an acknowledge after the reception of each byte that has been clocked out of the slave transmitter. The device that acknowledges has to pull down the SDA line during the acknowledge clock pulse, so that the SDA line is stable LOW during the HIGH period of the acknowledge related clock pulse; set-up time and hold time must be taken into account. A master receiver must signal an end of data to the transmitter by not generating an acknowledge on the last byte that has been clocked out of the slave. In this event, the transmitter must leave the data line HIGH to enable the master to generate a STOP condition.
data output by transmitter not acknowledge data output by receiver acknowledge SCL from master S START condition 1 2 8 clock pulse for acknowledgement
002aaa987
9
Fig 18. Acknowledgement on the I2C-bus
PCA9555_8
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Product data sheet
Rev. 08 -- 22 October 2009
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NXP Semiconductors
PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
8. Application design-in information
VDD (5 V) VDD MASTER CONTROLLER SCL SDA
10 k
10 k
10 k
2 k
SUB-SYSTEM 1 (e.g., temp sensor) INT
VDD
PCA9555
SCL SDA IO0_0 IO0_1 IO0_2 IO0_3 SUB-SYSTEM 2 (e.g., counter) RESET A ENABLE controlled switch (e.g., CBT device) B IO0_6 IO0_7 IO1_0 IO1_1 IO1_2 IO1_3 IO1_4 IO1_5 IO1_6 IO1_7 VSS SUB-SYSTEM 3 (e.g., alarm system) 10 DIGIT NUMERIC KEYPAD ALARM
INT GND
INT
IO0_4 IO0_5
A2 A1 A0
VDD
002aac704
Device address configured as 0100 000xb for this example. IO0_0, IO0_2, IO0_3 configured as outputs. IO0_1, IO0_4, IO0_5 configured as inputs. IO0_6, IO0_7, and IO1_0 to IO1_7 configured as inputs.
Fig 19. Typical application
PCA9555_8
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Product data sheet
Rev. 08 -- 22 October 2009
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NXP Semiconductors
PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
9. Limiting values
Table 13. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VDD VI/O IO II IDD ISS Ptot Tstg Tamb Parameter supply voltage voltage on an input/output pin output current input current supply current ground supply current total power dissipation storage temperature ambient temperature operating on an I/O pin Conditions Min -0.5 VSS - 0.5 -65 -40 Max +6.0 6 50 20 160 200 200 +150 +85 Unit V V mA mA mA mA mW C C
PCA9555_8
(c) NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 08 -- 22 October 2009
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NXP Semiconductors
PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
10. Static characteristics
Table 14. Static characteristics VDD = 2.3 V to 5.5 V; VSS = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Supplies VDD IDD Istb supply voltage supply current standby current Operating mode; VDD = 5.5 V; no load; fSCL = 100 kHz Standby mode; VDD = 5.5 V; no load; VI = VSS; fSCL = 0 kHz; I/O = inputs Standby mode; VDD = 5.5 V; no load; VI = VDD; fSCL = 0 kHz; I/O = inputs VPOR VIL VIH IOL IL Ci I/Os VIL VIH IOL VOH LOW-level input voltage HIGH-level input voltage LOW-level output current VDD = 2.3 V to 5.5 V; VOL = 0.5 V VDD = 2.3 V to 5.5 V; VOL = 0.7 V HIGH-level output voltage IOH = -8 mA; VDD = 2.3 V IOH = -10 mA; VDD = 2.3 V IOH = -8 mA; VDD = 3.0 V IOH = -10 mA; VDD = 3.0 V IOH = -8 mA; VDD = 4.75 V IOH = -10 mA; VDD = 4.75 V ILIH ILIL Ci Co IOL VIL VIH ILI
[1]
[2] [2] [3] [3] [3] [3] [3] [3]
Parameter
Conditions
Min 2.3 -0.5 0.7VDD
Typ 135 1.1 0.25 1.5 6 (8 to 20) 3.7 3.7 -
Max 5.5 200 1.5 1 1.65
Unit V A mA A V
power-on reset voltage[1] LOW-level input voltage HIGH-level input voltage LOW-level output current leakage current input capacitance
no load; VI = VDD or VSS
Input SCL; input/output SDA +0.3VDD V 5.5 +1 10 V mA A pF
VOL = 0.4 V VI = VDD = VSS VI = VSS
3 -1 -0.5 0.7VDD 8 10 1.8 1.7 2.6 2.5 4.1 4.0 -
+0.3VDD V 5.5 1 -100 5 5 V mA mA V V V V V V A A pF pF mA
(10 to 24) -
HIGH-level input leakage current LOW-level input leakage current input capacitance output capacitance LOW-level output current LOW-level input voltage HIGH-level input voltage input leakage current
VDD = 5.5 V; VI = VDD VDD = 5.5 V; VI = VSS
Interrupt INT VOL = 0.4 V 3 -0.5 0.7VDD -1 Select inputs A0, A1, A2 +0.3VDD V 5.5 +1 V A
VDD must be lowered to 0.2 V for at least 5 s in order to reset part.
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16-bit I2C-bus and SMBus I/O port with interrupt
[2] [3]
Each I/O must be externally limited to a maximum of 25 mA and each octal (IO0_0 to IO0_7 and IO1_0 to IO1_7) must be limited to a maximum current of 100 mA for a device total of 200 mA. The total current sourced by all I/Os must be limited to 160 mA.
6.0 VOH (V) 5.0
002aac706
4.5 VOH (V) 3.5
002aac707
(1) (2)
4.0
(1)
2.5
3.0
(2)
2.0 2.7
3.6 VDD (V)
5.5
1.5 2.3
3.0 VDD (V)
4.75
(1) IOH = -8 mA (2) IOH = -10 mA
(1) IOH = -8 mA (2) IOH = -10 mA
Fig 20. VOH maximum
1.6 IDD (mA) 1.2
Fig 21. VOH minimum
002aac705
(1) (2) (3)
0.8
0.4
0 all 1s one 0 three 0s all 0s number of I/Os
VDD = 5.5 V; VI/O = 5.5 V; A2, A1, A0 set to logic 0. (1) Tamb = -40 C (2) Tamb = +25 C (3) Tamb = +85 C
Fig 22. IDD versus number of I/Os held LOW
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16-bit I2C-bus and SMBus I/O port with interrupt
11. Dynamic characteristics
Table 15. Symbol Dynamic characteristics Parameter Conditions Standard-mode I2C-bus Min fSCL tBUF tHD;STA tSU;STA tSU;STO tVD;ACK tHD;DAT tVD;DAT tSU;DAT tLOW tHIGH tf tr tSP SCL clock frequency bus free time between a STOP and START condition hold time (repeated) START condition set-up time for a repeated START condition set-up time for STOP condition data valid acknowledge time data hold time data valid time data set-up time LOW period of the SCL clock HIGH period of the SCL clock fall time of both SDA and SCL signals rise time of both SDA and SCL signals pulse width of spikes that must be suppressed by the input filter data output valid time data input set-up time data input hold time valid time on pin INT reset time on pin INT
[2] [1]
Fast-mode I2C-bus Min 0 1.3 0.6 0.6 0.6 0.1 0 50 100 1.3 0.6 20 + 0.1Cb[3] 20 + 0.1Cb[3] Max 400 0.9 300 300 50
Unit
Max 100 3.45 300 1000 50
0 4.7 4.0 4.7 4.0 0.3 0 300 250 4.7 4.0 -
kHz s s s s s ns ns ns s s ns ns ns
Port timing tv(Q) tsu(D) th(D) tv(INT_N) trst(INT_N)
[1] [2] [3]
150 1 -
200 4 4
150 1 -
200 4 4
ns ns s s s
Interrupt timing
tVD;ACK = time for acknowledgement signal from SCL LOW to SDA (out) LOW. tVD;DAT = minimum time for SDA data out to be valid following SCL LOW. Cb = total capacitance of one bus line in pF.
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SDA tBUF tLOW SCL tr tf tHD;STA tSP
tHD;STA P S tHD;DAT tHIGH tSU;DAT Sr
tSU;STA
tSU;STO P
002aaa986
Fig 23. Definition of timing on the I2C-bus
12. Test information
VDD open GND
VDD PULSE GENERATOR VI DUT
RT
VO
RL 500
CL 50 pF
002aab284
RL = load resistor. CL = load capacitance includes jig and probe capacitance. RT = termination resistance should be equal to the output impedance of Zo of the pulse generators.
Fig 24. Test circuitry for switching times
RL
S1
from output under test
CL 50 pF
500 RL 500
2VDD open GND
002aac226
Fig 25. Load circuit
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16-bit I2C-bus and SMBus I/O port with interrupt
13. Package outline
DIP24: plastic dual in-line package; 24 leads (600 mil) SOT101-1
seating plane
D
ME
A2
A
L
A1 c Z e b1 b 24 13 MH wM (e 1)
pin 1 index E
1
12
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 5.1 0.2 A1 min. 0.51 0.02 A2 max. 4 0.16 b 1.7 1.3 0.066 0.051 b1 0.53 0.38 0.021 0.015 c 0.32 0.23 0.013 0.009 D (1) 32.0 31.4 1.26 1.24 E (1) 14.1 13.7 0.56 0.54 e 2.54 0.1 e1 15.24 0.6 L 3.9 3.4 0.15 0.13 ME 15.80 15.24 0.62 0.60 MH 17.15 15.90 0.68 0.63 w 0.25 0.01 Z (1) max. 2.2 0.087
Note 1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included. OUTLINE VERSION SOT101-1 REFERENCES IEC 051G02 JEDEC MO-015 JEITA SC-509-24 EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-13
Fig 26. Package outline SOT101-1 (DIP24)
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16-bit I2C-bus and SMBus I/O port with interrupt
SO24: plastic small outline package; 24 leads; body width 7.5 mm
SOT137-1
D
E
A X
c y HE vMA
Z 24 13
Q A2 A1 pin 1 index Lp L 1 e bp 12 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.1 A1 0.3 0.1 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 15.6 15.2 0.61 0.60 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.05 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 Z
(1)
0.9 0.4
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
0.035 0.004 0.016
8 o 0
o
Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. OUTLINE VERSION SOT137-1 REFERENCES IEC 075E05 JEDEC MS-013 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 27. Package outline SOT137-1 (SO24)
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16-bit I2C-bus and SMBus I/O port with interrupt
SSOP24: plastic shrink small outline package; 24 leads; body width 5.3 mm
SOT340-1
D
E
A X
c y HE vMA
Z 24 13
Q A2 pin 1 index A1 (A 3) Lp L 1 e bp 12 wM detail X A
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 2 A1 0.21 0.05 A2 1.80 1.65 A3 0.25 bp 0.38 0.25 c 0.20 0.09 D (1) 8.4 8.0 E (1) 5.4 5.2 e 0.65 HE 7.9 7.6 L 1.25 Lp 1.03 0.63 Q 0.9 0.7 v 0.2 w 0.13 y 0.1 Z (1) 0.8 0.4 8 o 0
o
Note 1. Plastic or metal protrusions of 0.2 mm maximum per side are not included. OUTLINE VERSION SOT340-1 REFERENCES IEC JEDEC MO-150 JEITA EUROPEAN PROJECTION
ISSUE DATE 99-12-27 03-02-19
Fig 28. Package outline SOT340-1 (SSOP24)
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PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
TSSOP24: plastic thin shrink small outline package; 24 leads; body width 4.4 mm
SOT355-1
D
E
A
X
c y HE vMA
Z
24
13
Q A2 pin 1 index A1 (A 3) A
Lp L
1
e bp
12
wM detail X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.15 0.05 A2 0.95 0.80 A3 0.25 bp 0.30 0.19 c 0.2 0.1 D (1) 7.9 7.7 E (2) 4.5 4.3 e 0.65 HE 6.6 6.2 L 1 Lp 0.75 0.50 Q 0.4 0.3 v 0.2 w 0.13 y 0.1 Z (1) 0.5 0.2 8o 0o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT355-1 REFERENCES IEC JEDEC MO-153 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19
Fig 29. Package outline SOT355-1 (TSSOP24)
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16-bit I2C-bus and SMBus I/O port with interrupt
HVQFN24: plastic thermal enhanced very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.85 mm
SOT616-1
D
B
A
terminal 1 index area A A1 E c
detail X
e1
1/2 e
C b 12 vMCAB wMC 13 e y1 C y
e 7 L 6
Eh
1/2 e
e2
1
18
terminal 1 index area
24 Dh 0
19 X 2.5 scale 5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max. 1 A1 0.05 0.00 b 0.30 0.18 c 0.2 D (1) 4.1 3.9 Dh 2.25 1.95 E (1) 4.1 3.9 Eh 2.25 1.95 e 0.5 e1 2.5 e2 2.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT616-1 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 01-08-08 02-10-22
Fig 30. Package outline SOT616-1 (HVQFN24)
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PCA9555
16-bit I2C-bus and SMBus I/O port with interrupt
HWQFN24: plastic thermal enhanced very very thin quad flat package; no leads; 24 terminals; body 4 x 4 x 0.75 mm
SOT994-1
D
B
A
terminal 1 index area E A A1 c
detail X
e1 1/2 e e
7
b
12
v w
M M
CAB C
C y1 C y
L
6 13
e
Eh 1/2 e
1
e2
18
terminal 1 index area
24
19
Dh
X
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A(1) max 0.8 A1 0.05 0.00 b 0.30 0.18 c 0.2 D(1) 4.1 3.9 Dh 2.25 1.95 E (1) 4.1 3.9 Eh 2.25 1.95 e 0.5 e1 2.5 e2 2.5 L 0.5 0.3 v 0.1 w 0.05 y 0.05 y1 0.1
Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. OUTLINE VERSION SOT994-1 REFERENCES IEC --JEDEC MO-220 JEITA --EUROPEAN PROJECTION ISSUE DATE 07-02-07 07-03-03
Fig 31. Package outline SOT994-1 (HWQFN24)
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14. Handling information
All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling ensure that the appropriate precautions are taken as described in JESD625-A or equivalent standards.
15. Soldering of SMD packages
This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 "Surface mount reflow soldering description".
15.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.
15.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:
* Through-hole components * Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
* * * * * *
Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering
15.3 Wave soldering
Key characteristics in wave soldering are:
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16-bit I2C-bus and SMBus I/O port with interrupt
* Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are exposed to the wave
* Solder bath specifications, including temperature and impurities 15.4 Reflow soldering
Key characteristics in reflow soldering are:
* Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 32) than a SnPb process, thus reducing the process window
* Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
* Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 16 and 17
Table 16. SnPb eutectic process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 2.5 2.5 Table 17. 235 220 Lead-free process (from J-STD-020C) Package reflow temperature (C) Volume (mm3) < 350 < 1.6 1.6 to 2.5 > 2.5 260 260 250 350 to 2000 260 250 245 > 2000 260 245 245 350 220 220
Package thickness (mm)
Package thickness (mm)
Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 32.
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16-bit I2C-bus and SMBus I/O port with interrupt
temperature
maximum peak temperature = MSL limit, damage level
minimum peak temperature = minimum soldering temperature
peak temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 32. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365 "Surface mount reflow soldering description".
16. Soldering of through-hole mount packages
16.1 Introduction to soldering through-hole mount packages
This text gives a very brief insight into wave, dip and manual soldering. Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board.
16.2 Soldering by dipping or by solder wave
Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Typical dwell time of the leads in the wave ranges from 3 seconds to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit.
16.3 Manual soldering
Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 C and 400 C, contact may be up to 5 seconds.
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16-bit I2C-bus and SMBus I/O port with interrupt
16.4 Package related soldering information
Table 18. Package CPGA, HCPGA DBS, DIP, HDIP, RDBS, SDIP, SIL PMFP[2]
[1] [2]
Suitability of through-hole mount IC packages for dipping and wave soldering Soldering method Dipping suitable Wave suitable suitable[1] not suitable
For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. For PMFP packages hot bar soldering or manual soldering is suitable.
17. Abbreviations
Table 19. Acronym CMOS GPIO I2C-bus SMBus I/O ACPI LED ESD HBM MM CDM PCB FET MSB LSB Abbreviations Description Complementary Metal Oxide Semiconductor General Purpose Input/Output Inter-Integrated Circuit bus System Management Bus Input/Output Advanced Configuration and Power Interface Light Emitting Diode ElectroStatic Discharge Human Body Model Machine Model Charged Device Model Printed-Circuit Board Field-Effect Transistor Most Significant Bit Least Significant Bit
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18. Revision history
Table 20. Revision history Release date 20091022 Data sheet status Product data sheet Change notice Supersedes PCA9555_7 Document ID PCA9555_8 Modifications:
* * * * *
Table 2 "Ordering options", Topside mark for TSSOP24 package, PCA9555PW, is changed from "PCA9555PW" to "PCA9555" Figure 13 "Read Input port register, scenario 1" modified Figure 14 "Read Input port register, scenario 2" modified Table 14 "Static characteristics", Table note [1] modified (added phrase "for at least 5 s") updated soldering information Product data sheet Product data sheet Product data sheet Product data sheet Product data Product data Product data 853-2252 28672 of 2002 July 26 PCA9555_6 PCA9555_5 PCA9555_4 PCA9555_3 PCA9555_2 PCA9555_1 -
PCA9555_7 PCA9555_6 PCA9555_5 (9397 750 14125) PCA9555_4 (9397 750 13271) PCA9555_3 (9397 750 10164) PCA9555_2 (9397 750 09818) PCA9555_1 (9397 750 08343)
20070605 20060825 20040930 20040727 20020726 20020513 20010507
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16-bit I2C-bus and SMBus I/O port with interrupt
19. Legal information
19.1 Data sheet status
Document status[1][2] Objective [short] data sheet Preliminary [short] data sheet Product [short] data sheet
[1] [2] [3]
Product status[3] Development Qualification Production
Definition This document contains data from the objective specification for product development. This document contains data from the preliminary specification. This document contains the product specification.
Please consult the most recently issued document before initiating or completing a design. The term `short data sheet' is explained in section "Definitions". The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.
19.2 Definitions
Draft -- The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet -- A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer's own risk. Applications -- Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values -- Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale -- NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license -- Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control -- This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities.
19.3 Disclaimers
General -- Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes -- NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use -- NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental
19.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus -- logo is a trademark of NXP B.V.
20. Contact information
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com
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16-bit I2C-bus and SMBus I/O port with interrupt
21. Contents
1 2 3 3.1 4 5 5.1 5.2 6 6.1 6.2 6.2.1 6.2.2 6.2.3 6.2.4 6.2.5 6.3 6.4 6.5 6.5.1 6.5.2 6.5.3 7 7.1 7.1.1 7.2 7.3 8 9 10 11 12 13 14 15 15.1 15.2 15.3 15.4 16 16.1 16.2 16.3 16.4 General description . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 Ordering options . . . . . . . . . . . . . . . . . . . . . . . . 2 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 Functional description . . . . . . . . . . . . . . . . . . . 6 Device address . . . . . . . . . . . . . . . . . . . . . . . . . 6 Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Command byte . . . . . . . . . . . . . . . . . . . . . . . . . 6 Registers 0 and 1: Input port registers . . . . . . . 7 Registers 2 and 3: Output port registers. . . . . . 7 Registers 4 and 5: Polarity Inversion registers . 7 Registers 6 and 7: Configuration registers . . . . 8 Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . 8 I/O port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Bus transactions . . . . . . . . . . . . . . . . . . . . . . . . 9 Writing to the port registers . . . . . . . . . . . . . . . 9 Reading the port registers . . . . . . . . . . . . . . . 11 Interrupt output . . . . . . . . . . . . . . . . . . . . . . . . 14 Characteristics of the I2C-bus. . . . . . . . . . . . . 14 Bit transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 START and STOP conditions . . . . . . . . . . . . . 14 System configuration . . . . . . . . . . . . . . . . . . . 15 Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . 15 Application design-in information . . . . . . . . . 16 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 17 Static characteristics. . . . . . . . . . . . . . . . . . . . 18 Dynamic characteristics . . . . . . . . . . . . . . . . . 20 Test information . . . . . . . . . . . . . . . . . . . . . . . . 21 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 22 Handling information. . . . . . . . . . . . . . . . . . . . 28 Soldering of SMD packages . . . . . . . . . . . . . . 28 Introduction to soldering . . . . . . . . . . . . . . . . . 28 Wave and reflow soldering . . . . . . . . . . . . . . . 28 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 28 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 29 Soldering of through-hole mount packages . 30 Introduction to soldering through-hole mount packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Soldering by dipping or by solder wave . . . . . 30 Manual soldering . . . . . . . . . . . . . . . . . . . . . . 30 Package related soldering information . . . . . . 31 17 18 19 19.1 19.2 19.3 19.4 20 21 Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . Revision history . . . . . . . . . . . . . . . . . . . . . . . Legal information . . . . . . . . . . . . . . . . . . . . . . Data sheet status . . . . . . . . . . . . . . . . . . . . . . Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . Contact information . . . . . . . . . . . . . . . . . . . . Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 32 33 33 33 33 33 33 34
Please be aware that important notices concerning this document and the product(s) described herein, have been included in section `Legal information'.
(c) NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 22 October 2009 Document identifier: PCA9555_8

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